The present invention relates to the deposition of dielectric layers during wafer processing and more specifically to a method and apparatus for forming an interconductor oxide layer having a low dielectric constant.
One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by a chemical vapor deposition (CVD) process. There are different types of CVD processes, such as plasma-enhanced CVD (PECVD) processes and thermal CVD processes. In a typical PECVD process, a plasma of reactive species is formed from gases and the reactive species form a film on the substrate. In a typical thermal CVD process, gases react on a heated surface of a substrate to form the desired film. Each type of CVD process has attributes that may be desirable or undesirable for different applications, and it may be desirable to sequentially use both types of processes to take advantage of a combination of their beneficial attributes.
Semiconductor device geometries have dramatically decreased in size since integrated circuits were first introduced several decades ago. Since then, the number of devices that will fit on an integrated circuit, or chip, of a given size has regularly doubled every year or two. Today""s wafer fabrication plants are routinely producing devices with 0.35-micron feature sizes, and tomorrow""s plants soon will be producing devices having even smaller geometries.
As device sizes become smaller and integration density increases, new problems arise that were not as important with the former technology. For example, the problem of interlevel xe2x80x9ccrosstalkxe2x80x9d, which is the undesired coupling of an electrical signal on one metal layer onto another metal layer, arose with the advent of multilevel metal technology, in which two or more layers of metal with intervening insulating, or dielectric, layers are formed on a semiconductor substrate. Crosstalk can be reduced by moving the metal layers further apart, minimizing the areas of overlapping metal between metal layers, reducing the dielectric constant of the material between metal layers, and combinations of these and other methods.
Undesired coupling of electrical signals can also occur between adjacent conductive traces, or lines, within a conductive layer. As device geometries shrink, the conductive lines become closer together and it becomes more important to isolate them from each other.
Another issue rising in importance with decreasing geometry is the xe2x80x9cRC time constantxe2x80x9d of a particular trace. Each trace has a resistance, R, that is a product of its cross section and bulk resistivity, among other factors, and a capacitance, C, that is a product of the surface area of the trace and the dielectric constant of the material or space surrounding the trace, among other factors. If a voltage is applied to one end of the conductive trace, charge does not immediately build up on the trace because of the RC time constant. Similarly, if a voltage is removed from a trace, the trace does not immediately drain to zero. Thus, high RC time constants can slow down the operation of a circuit. Unfortunately, shrinking circuit geometries produce narrower traces, which results in a higher resistivity. Therefore it is important to reduce the capacitance of the trace, such as by reducing the dielectric constant of the surrounding material or material between traces, to maintain or reduce the RC time constant.
Many approaches have been proposed for obtaining lower dielectric constants. One approach incorporates a halogen, such as fluorine, into a silicon oxide layer to form a silicon-oxygen-halogen network. It is believed that fluorine, a highly electronegative species, lowers the dielectric constant of the resulting layer by decreasing the polarizability of the silicon-oxygen-fluorine network. However, using fluorine might cause problems, such as corrosion, in some applications. Therefore, in some instances it is desirable to lower the dielectric constant of a dielectric layer on a semiconductor substrate without using a halogen, or to use even further lower the dielectric constant by using a halogen in combination with other methods.
The present invention provides a method and an apparatus for producing a low-dielectric-constant layer for use between conductive traces and/or between conductive layers of a semiconductor device. Specifically, the present invention achieves a low-dielectric-constant layer of silicon oxide by intentionally introducing porosity into the layer using a combination of deposition techniques and an intervening surface treatment.
According to one aspect of the invention, a first layer of silicon oxide is formed on a substrate using a PECVD process, the surface of the first layer is treated with activated oxygen to enhance its surface sensitivity, and a second layer of silicon oxide is deposited using a thermal CVD method, such as a subatmospheric CVD (SACVD) method. A hydrophobic silicon source, such as tetraethylorthosilane (TEOS), is used during the thermal CVD method to form a porous layer of SACVD silicon oxide. In one embodiment of the invention, the surface sensitivity of the PECVD layer is enhanced by exposing the surface to ozone (O3) for a period of time. In another embodiment, the surface sensitivity is enhanced by exposing the surface to an oxygen-based plasma of the proper density and intensity to eliminate dangling silicon bonds on the surface of the PECVD layer.
In a further embodiment, fluorine is incorporated into the PECVD layer to reduce the dielectric constant of that layer and to enhance the hydrophilic characteristics of the surface of that layer. The SACVD layer may be thermally or plasma-treated after formation to improve the quality of the surface of the SACVD layer, and a capping layer may be deposited over the SACVD layer in addition, or as an alternative, to the surface treatment of the SACVD layer.